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T T DU C PR O A C EM EN ET E E PL OL O B S N D ED R B MME HC5504 EC O RData Sheet
HC-5504B1
August 2003 FN4125.4
ITU Low Cost, PABX SLIC With 40mA Loop Feed
The Intersil SLIC incorporates many of the BORSHT functions on a single IC chip. This includes DC battery feed, a ring relay driver, supervisory and hybrid functions. This device is designed to maintain transmission performance in the presence of externally induced longitudinal currents. Using the unique Intersil dielectric isolation process, the SLIC can operate directly with a wide range of station battery voltages. The SLIC also provides selective denial of power. If the PBX system becomes overloaded during an emergency, the SLIC will provide system protection by denying power to selected subscriber loops. The Intersil SLIC is ideally suited for the design of new digital PBX systems by eliminating bulky hybrid transformers.
Features
* Low Cost Version of the HC-5504B * Capable of 5V or 12V (VB+) Operation * Monolithic Integrated Device * DI High Voltage Process * Compatible With Worldwide PBX Performance Requirements * Controlled Supply of Battery Feed Current for Short Loops (41mA) * Internal Ring Relay Driver * Allows Interfacing With Negative Superimposed Ringing Systems * Low Power Consumption During Standby * Switch Hook Ground Key and Ring Trip Detection Functions * Selective Denial of Power to Subscriber Loops
Part Number Information
PART NUMBER HC4P5504B1-5 TEMP. RANGE (oC) 0 to 75 PACKAGE 28 Ld PLCC PKG. DWG. # N28.45
Applications
* Solid State Line Interface Circuit for Analog and Digital PBX Systems * Direct Inward Dial (DID) Trunks * Voice Messaging PBXs * Related Literature - AN549, The HC-5502S/4X Telephone Subscriber Line Interface Circuits (SLIC) - AN571, Using Ring Sync with HC-5502A and HC-5504 SLICs
Pinout
HC-5504B1 (PLCC) TOP VIEW
RFS RING TIP N/C TX AG 27 C4 26
4
3
2
1
28
VB+ C3 DG N/C RS
5 6 7 8 9
25 RX 24 +IN 23 -IN 22 N/C 21 OUT 20 C2 19 RC
RD 10 TF 11
12 RF
13 VB-
14 BG
15 N/C
16 SHD
17 GKD
18 PD
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HC-5504B1
Absolute Maximum Ratings (Note 1)
Maximum Continuous Supply Voltages (VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to 0.5V (VB+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V (VB+ - VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75V Relay Drive Voltage (VRD). . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V
Thermal Information
Thermal Resistance (Typical, Note 2)
JA (oC/W)
28 Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (PLCC - Lead Tips Only)
Operating Conditions
Operating Temperature Range HC-5504B1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Relay Driver Voltage (VRD) . . . . . . . . . . . . . . . . . . . . . . . . 5V to 12V Positive Supply Voltage (VB+) . . . 4.75V to 5.25V or 10.8V to 13.2V Negative Supply Voltage (VB-) . . . . . . . . . . . . . . . . . . . -42V to -58V High Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V Low Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V Loop Resistance (RL) . . . . . . . . . . . . . . . . . . . . . . . .200 to 1200
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 x 102 Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connected Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER On Hook Power Dissipation Off Hook Power Dissipation Off Hook IB+ Off Hook IBOff Hook Loop Current Off Hook Loop Current Off Hook Loop Current Fault Currents TIP to Ground RING to Ground TIP to RING TIP and RING to Ground Ring Relay Drive VOL Ring Relay Driver Off Leakage Ring Trip Detection Period Switch Hook Detection Threshold
Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters TA = 25oC. Min-Max Parameters are Over Operating Temperature Range CONDITIONS ILONG = 0 (Note 2), VB+ = 12V RL = 600 , ILONG = 0 (Note 3), VB+ = 12V RL = 600 , ILONG = 0 (Note 3), TA = 25oC RL = 600, ILONG = 0 (Note 3) RL = 1200 , ILONG = 0 (Note 3) RL = 1200 , VB- = -42V, ILONG = 0 (Note 3) TA = 25oC RL = 200 , ILONG = 0 (Note 3) MIN 17.5 36 TYP 170 425 35 21 41 MAX 235 550 5.3 41 48 UNITS mW mW mA mA mA mA mA
IOL = 62mA VRD = 12V, RC = 1 = HIGH, TA = 25oC RL = 600 SHD = VOL SHD = VOH 10 20 0
14 55 41 55 0.2 2 2 -
0.5 100 3 5 10 5
mA mA mA mA V A Ring Cycles mA mA mA mA mA ms
Ground Key Detection Threshold
GKD = VOL GKD = VOH
Loop Current During Power Denial Dial Pulse Distortion
RL = 200
2
HC-5504B1
Electrical Specifications
PARAMETER Receive Input Impedance Transmit Output Impedance 2-Wire Return Loss SRL LO ERL SRL HI Longitudinal Balance 2-Wire Off Hook 2-Wire On Hook 4-Wire Off Hook Low Frequency Longitudinal Balance R.E.A. Method, (Note 4), RL = 600 0oC TA 75oC At 1kHz, 0dBm Input Level, Referenced 600 200 - 3400Hz Referenced to Absolute Loss at 1kHz and 0dBm Signal Level (Note 4) (Note 4) Absolute Delay 2-Wire to 4-Wire, 4-Wire to 2-Wire Trans Hybrid Loss Overload Level 2-Wire to 4-Wire, 4-Wire to 2-Wire Level Linearity 2-Wire to 4-Wire, 4-Wire to 2-Wire Balance Network Set Up for 600 Termination at 1kHz VB+ = +5V VB+ = 12V At 1kHz, (Note 4) Referenced to 0dBm Level +3 to -40dBm -40 to -50dBm -50 to -55dBm Power Supply Rejection Ratio VB+ to 2-Wire VB+ to Transmit VB- to 2-Wire VB- to Transmit VB+ to 2-Wire VB+ to Transmit VB- to 2-Wire VB- to Transmit Logic Input Current (RS, RC, PD) 0V VIN 5V 200 - 16kHz, RL = 600 (Note 4) 30 - 60Hz, RL = 600 15 15 15 15 30 30 30 30 100 dB dB dB dB dB dB dB dB A 0.05 0.1 0.3 dB dB dB (Note 4) 30 1.5 1.75 40 2 ms dB VPEAK VPEAK 1 -89 5 -85 dBrnC dBm0p 0.05 0.02 0.2 0.05 dB dB 1VRMS 200Hz - 3400Hz, (Note 4) IEEE Method 0oC TA 75oC (Note 4) (Note 4) (Referenced to 600 + 2.16F), (Note 4) 15.5 24 31 dB dB dB Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters TA = 25oC. Min-Max Parameters are Over Operating Temperature Range (Continued) CONDITIONS MIN TYP 110 10 MAX 20 UNITS k
53 53 50 -
58 58 58 -
23 -67
dB dB dB dBrnC dBm0p
Insertion Loss 2-Wire to 4-Wire, 4-Wire to 2-Wire Frequency Response Idle Channel Noise 2-Wire to 4-Wire, 4-Wire to 2-Wire
3
HC-5504B1
Electrical Specifications
PARAMETER Logic Inputs Logic `0' VIL Logic `1' VIH Logic Outputs Logic `0' VOL Logic `1' VOH ILOAD 800A, VB+ = 12V, 5V ILOAD 80A, VB+ = 12V ILOAD 40A, VB+ = 5V 2.7 2.7 0.1 5.0 0.5 5.5 5.0 V V V 2.0 0.8 5.5 V V Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters TA = 25oC. Min-Max Parameters are Over Operating Temperature Range (Continued) CONDITIONS MIN TYP MAX UNITS
Uncommitted Op Amp Specifications
PARAMETER Input Offset Voltage Input Offset Current Input Bias Current Differential Input Resistance Output Voltage Swing (Note 4) RL = 10K, VB+ = 12V RL = 10K, VB+ = 5V Output Resistance Small Signal GBW NOTES: 3. ILONG = Longitudinal Current. 4. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance. AVCL = 1 (Note 4) (Note 4) CONDITIONS MIN TYP 5 10 20 1 6.2 3 10 1 MAX 6.6 UNITS mV nA nA M VPEAK VPEAK MHz
4
HC-5504B1 Pin Descriptions
28 PIN PLCC 2 SYMBOL TIP DESCRIPTION An analog input connected to the TIP (more positive) side of the subscriber loop through a 150 feed resistor and a ring relay contact. Functions with the Ring terminal to receive voice signals from the telephone and for loop monitoring purposes. An analog input connected to the RING (more negative) side of the subscriber loop through a 150 feed resistor and a ring relay contact. Functions with the Tip terminal to receive voice signals from the telephone and for loop monitoring purposes. Senses ring side of loop for ground key and ring trip detection. During ringing, the ring signal is inserted into the line at this node and RF is isolated from RFS via a relay. Positive Voltage Source - Most positive supply. VB+ is typically 12V or 5V. Capacitor #3 - An external capacitor to be connected between this terminal and analog ground. Required for proper operation of the loop current limiting function, and for filtering VB-. Typical value is 0.3F, 30V. Digital Ground - To be connected to zero potential and serves as a reference for all digital inputs and outputs on the SLIC microcircuit. Ring Synchronization Input - A TTL - compatible clock input. The clock should be arranged such that a positive pulse transition occurs on the zero crossing of the ring voltage source, as it appears at the RFS terminal. For Tip side injected systems, the RS pulse should occur on the negative going zero crossing and for Ring injected systems, on the positive going zero crossing. This ensures that the ring relay activates and deactivates when the instantaneous ring voltage is near zero. If synchronization is not required, the pin should be tied to 5V. Relay Driver - A low active open collector logic output. When enabled, the external ring relay is energized. Tip Feed - A low impedance analog output connected to the TIP terminal through a 150 feed resistor. Functions with the RF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. Ring Feed - A low impedance analog output connected to the RING terminal through a 150 feed resistor. Functions with the TF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. Negative Voltage Source - Most negative supply. VB- is typically -48V with an operational range of -42V to -58V. Frequently referred to as "battery". Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this ground terminal. Switch Hook Detection - A low active LS TTL-compatible logic output. This output is enabled for loop currents exceeding 10mA and disabled for loop currents less than 5mA. Ground Key Detection - A low active LS TTL-compatible logic output. This output is enabled if the DC current into the ring lead exceeds the DC current out of the tip lead by more than 20mA, and disabled if this current difference is less than 10mA. Power Denial - A low active TTL - Compatible logic input. When enabled, the switch hook detect (SHD) and ground key detect (GKD) are not necessarily valid, and the relay driver (RD) output is disabled. Ring Command - A low active TTL - Compatible logic input. When enabled, the relay driver (RD) output goes low on the next high level of the ring sync (RS) input, as long as the SLIC is not in the power denial state (PD = 0) or the subscriber is not already off- hook (SHD = 0). Capacitor #2 - An external capacitor to be connected between this terminal and digital ground. Prevents false ground key indications from occurring during ring trip detection. Typical value is 0.15F, 10V. This capacitor is not used if ground key function is not required and (Pin 17) may be left open or connected to digital ground. The analog output of the spare operational amplifier. The output voltage swing is typically 5V. The inverting analog input of the spare operational amplifier. The non-inverting analog input of the spare operational amplifier. Receive Input, Four Wire Side - A high impedance analog input which is internally biased. Capacitive coupling to this input is required. AC signals appearing at this input differentially drive the Tip feed and Ring feed terminals, which in turn drive tip and ring through 300 of feed resistance on each side of the line.
3
RING
4 5 6 7 9
RFS VB+ C3 DG RS
10 11 12 13 14 16 17
RD TF RF VBBG SHD GKD
18 19
PD RC
20
C2
21 23 24 25
OUT -IN +IN RX
5
HC-5504B1 Pin Descriptions
28 PIN PLCC 26 SYMBOL C4 (Continued)
DESCRIPTION Capacitor #4 - An external capacitor to be connected between this terminal and analog ground. This capacitor prevents false ground key indication and false ring trip detection from occurring when longitudinal currents are induced onto the subscriber loop from near by power lines and other noise sources. This capacitor is also required for the proper operation of ring trip detection. Typical value is 0.5F, to 1.0F, 20V. This capacitor should be nonpolarized. Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX) and receive input (RX) terminals. Transmit Output, Four Wire Side - A low impedance analog output which represents the differential voltage across Tip and Ring. Transhybrid balancing must be performed (using the SLIC microcircuit's spare op amp) beyond this output to completely implement two to four wire conversion. This output is unbalanced and referenced to analog ground. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is essential. No internal connection.
27 28
AG TX
1, 8, 15, 22
NC
NOTE: All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first.
Functional Diagram
RS RC RD 1/2 RING RELAY TIP 150 150 2-WIRE LOOP SECONDARY PROTECTION BG VBRFS 1/2 RING RELAY RING 150 RING VOLTAGE V BRING PD SLIC MICROCIRCUIT -1 150 RX RECEIVE INPUT RF LOOP CURRENT LIMITER LINE DRIVERS TF VBBATTERY FEED +1 +IN + OP AMP OUT DIFF AMP + TX TRANSMIT OUTPUT RING CONTROL RING TRIP LOOP MONITORING SHD SWITCH HOOK DETECTION GKD GROUND KEY DETECTION TIP
RING SYNC RING COMMAND
-IN
POWER DENIAL
6
HC-5504B1 Schematic
SLIC FUNCTIONAL SCHEMATIC DIP/SOIC Pin Numbers Shown
21 RX 22 C4 11 VBAT 12 BAT GND 23 ANA GND VB+ VB1 VB2 VB3 VB4 VB5 5V 6 DIG GND 4 VB+ 20 19 18 OUT VB+
+
-
VOLTAGE AND CURRENT BIAS NETWORK
A-500 OP AMP
VBAT IB3
VB+ TF 9 VBAT
+ A-400 TIP FEED AMP IB4
R17 VB2 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 VBAT IB9 IB10 IB11
R12
RING TRIP DETECTOR 5V VB+ GK A-200 LONG'L I / V AMP + R11 VBAT IB7 R5 IB8 R20 + VBAT VB4 GND SHORTS CURRENT LIMITING IB1 GKD 14 5V IB10 VB+
R7 TIP 1 RING FEED SENSE 3 R8 R10 R9 VBAT R22 V + VBAT R23 B VB+ QD3 QD36
-
+ VB+ A-100 TRANSV'L I/V AMP SWITCH HOOK DETECTOR VB+ VBAT
+ VB3 STTL AND LOGIC INTERFACE
C2 17
R3 RING 2 R4 R1 R2 R16 R15 VB2
IB6
VBAT + R6 IB6 QD27 QD28 THERMAL LIMITING
SH
SHD 13
VB1
VBAT/2 REFERENCE R14
RC 16 RFC
R18
RF 10 VBAT IB5 A-300 RING FEED AMP +
R21
LOAD CURRENT LIMITING I B2
R19
VB5
VB5
PD 15
+
VBAT
R13 VBAT
VBAT
C3 5
TX 24
RS 7
RD 8
7
HC-5504B1 Schematic
(Continued) LOGIC GATE SCHEMATIC
C2
GK
1
2
LOGIC BIAS DELAY 6 4 8 3
5 7 9 12
SH
16 10
13 11 15 TTL TO STTL TTL TO STTL TTL TO STTL TO R21 C SCHOTTKY LOGIC 14 RELAY DRIVER
A B
C B A
STTL TO TTL
STTL TO TTL
RS
RC
PD
RD
SHD
GKD
Overvoltage Protection and Longitudinal Current Protection
The SLIC device, in conjunction with an external protection bridge, will withstand high voltage lightning surges and power line crosses. High voltage surge conditions are as specified in Table 1. The SLIC will withstand longitudinal currents up to a maximum or 30mARMS , 15mARMS per leg, without any performance degradation.
PARAMETER Longitudinal Surge Metallic Surge
TABLE 1. TEST CONDITION 10s Rise/ 1000s Fall 10s Rise/ 1000s Fall 10s Rise/ 1000s Fall 11 Cycles Limited to 10ARMS PERFORMANCE (MAX) 1000 (Plastic) 1000 (Plastic) 1000 (Plastic) UNITS VPEAK VPEAK VPEAK VRMS
T/GND R/GND 50/60Hz Current T/GND R/GND
700 (Plastic)
8
HC-5504B1 Applications Diagram
5V TO 12V 15 RS1 CS1 K1 SYSTEM CONTROLLER 13 14 7 16 BALANCE NETWORK 21 24 20 19 R3 18 17 5 22 + C4 C3 C2 + R2 C6 R1 ZB C5 C7 PCM SWITCHING FILTER/ NETWORK CODEC
TIP
K1A
RB1 RB2 (NOTE 5)
POWER SWITCH GROUND RING RING SYNC CMD DENIAL HOOK KEY 8 DETECT DETECT RD RX 1 TIP TX 9 SLIC TIP FEED +IN HC-5504B1 -IN OP AMP OUT RING FEED C2 C3 RING FEED SENSE NEG. BATT. 11 BATT. GND. C8 12 DIG. GND. 6 ANA. GND. 23 C4 VB+ C9 4
SUBSCRIBER LOOP
PRIMARY PROTECTION
VB K1B RS2 CS2 RB3 10 3 RB4 2 RING
RING PTC
-48V Z1 150VPEAK (MAX) RING GENERATOR
VB+
PIN NUMBERS GIVEN FOR DIP/SOIC PACKAGE.
-48V
FIGURE 1. TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC
Typical Component Values
C2 = 0.15F, 10V. C3 = 0.3F, 30V. C4 = 0.5F to 1.0F, 10%, 20V (Should be nonpolarized). C5 = 0.5F, 20V. C6 = C7 = 0.5F (10% Match Required) (Note 6). C8 = 0.01F, 100V. C9 = 0.01F, 20V, 20%. R1 = R2 = R3 = 100k (0.1% Match Required, 1% absolute value) ZB = 0 for 600 Terminations (Note 6). RB1 = RB2 = RB3 = RB4 = 150 (0.1% Match Required, 1% absolute value). RS1 = RS2 = 1k, typically. CS1 = CS2 = 0.1F, 200V typically, depending on VRING and line length. Z1 = 150V to 200V transient protection. PTC used as ring generator ballast.
NOTES: 5. Secondary protection diode bridge recommended is a 2A, 200V type. 6. To obtain the specified transhybrid loss it is necessary for the three legs of the balance network, C6-R1 and R2 and C7-ZB-R3, to match in impedance to within 0.3%. Thus, if C6 and C7 are 1F each, a 20% match is adequate. It should be noted that the transmit output to C6 sees a -22V step when the loop is closed. Too large a value for C6 may produce an excessively long transient at the op amp output to the PCM Filter/CODEC. 7. A 0.5F and 100k gives a time constant of 50ms. The uncommitted op amp output is internally clamped to stay within 6.6V and is current limited. 8. All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first. 9. Application shows Ring Injected Ringing, Balanced or Tip injected configuration may be used.
9
HC-5504B1 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP 0.004 (0.10) C
N28.45 (JEDEC MS-018AB ISSUE A) 28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
INCHES SYMBOL A A1 MIN 0.165 0.090 0.485 0.450 0.191 0.485 0.450 0.191 28 MAX 0.180 0.120 0.495 0.456 0.219 0.495 0.456 0.219 MILLIMETERS MIN 4.20 2.29 12.32 11.43 4.86 12.32 11.43 4.86 28 MAX 4.57 3.04 12.57 11.58 5.56 12.57 11.58 5.56 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97
0.025 (0.64) R 0.045 (1.14)
D2/E2 C L E1 E D2/E2 VIEW "A"
D D1 D2 E E1 E2 N
D1 D 0.020 (0.51) MAX 3 PLCS
A1 A
0.020 (0.51) MIN
SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53)
0.045 (1.14) MIN
0.025 (0.64) MIN VIEW "A" TYP.
NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. "N" is the number of terminal positions.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10

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